1. Field of the Invention
The present invention relates to a logic element constructed in accordance with current transfer technology having an emitter follower or, respectively, a plurality of emitter followers connected in parallel, as an input circuit and having at least one differential amplifier fed from a constant current source and comprising emitter-coupled transistors which are alternately blocked or rendered conductive.
2. Description of the Prior Art
Logic elements of the type set forth above are generally known in the art and are designated ECL and E.sup.2 CL logic circuits (cf. "Der Fernmelde-Ingenieur", No. 7, July 1973, pp. 20-21, particularly FIGS. 13 and 14, fully incorporated herein by this reference). Whereas emitter followers for the purpose of signal level shift precede the control inputs of the differential amplifiers, typical of the emitter-coupled logic in ECL circuits only in conjunction with so-called series coupling, a plurality of emitter followers are frequently connected in parallel in E.sup.2 CL circuits and are provided with a common emitter resistor. In addition to a signal level shift, the emitter followers then effect the inclusive-OR operation of a corresponding plurality of input signals. An exemplary embodiment of such a circuit is illustrated in FIG. 1.
A differential amplifier having the emitter-coupled transistors T1 and T2 and the collector load resistors R1 and R2 is fed with a constant current I.sub.D which is stablized by a constant current source consisting of a transistor T3 and an emitter resistor R3. The base of the constant current transistor T3 is connected to a first fixed potential VR1. The base of the transistor R1 of the differential amplifier is fixed by a second fixed reference potential VR2. The output signals Q and Q can be tapped at the junctions of the load resistors R1 and R2 with the collectors of the transistors T1 and T2 of the differential amplifier.
The aforementioned emitter follower typical of E.sup.2 CL logic elements for driving the base of the second transistor T2 of the differential amplifier consists of the transistor T4 and the emitter load resistor R4. An input signal E is applied to the base of the emitter follower transistor T4.
Given the series connection of a plurality of logic elements in current mode logic technology, ECL elements and E.sup.2 CL elements no longer differ in terms of the sequence of emitter follower and differential amplifier. A distinguishing criterion which is of no further interest in the present context, however, at most consists in the realization of inclusive-OR operations.
By way of addition, it should be pointed out that a high value resistor in comparison to the collector load resistors R1, R2 is frequently employed for the differential amplifier instead of a constant current source consisting of a transistor and an emitter resistor. On the other hand, the ohmic emitter resistor R4 in the emitter follower is occasionally replaced by a constant current source.
A current I.sub.E which has the direction for npn transistors, referenced in FIG. 1 by an arrow, is required for the discharge of the parasitic capacitance of the node A (FIG. 1) given a decreasing signal edge at the input E. When this bias current I.sub.E is absent due to an error in the manufacture of an integrated module, for example due to an interruption of the connecting lines to the emitter resistor R4, or if it has greatly reduced in comparison to the rated value, then the same can lead to a prolongation of the transfer of the output signals Q or, respectively, Q from one to the other binary signal level produced by a trailing edge of the input signal E which is increased by a factor of 100 and more without the fault being perceived in a static test because a differential amplifier just barely reacts correctly. The consequence is the necessity of introducing a high-cost dynamic check or the acceptance of the risk of a dynamic misbehavior of the circuit which has only been partially tested.